Field
Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon (a-Si) layers on a semiconductor substrate.
Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.25 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries. As device sizes continue to shrink, amorphous silicon thin films are used throughout many semiconductor integrated circuit manufacturing processes. Amorphous silicon thin films are used, for example, in the fabrication of three-dimensional devices, optoelectronic devices, gate electrodes, stack or trench capacitors, emitters, and contacts.
Current amorphous silicon thin films and methods for depositing these amorphous silicon thin films suffer from adhesion and bubbling problems. In addition, these amorphous silicon thin films and the related methods for deposition often lead to particle generation, which affects the quality of subsequently deposited films.
Therefore, there is a need in the art for an improved amorphous silicon layer and methods for depositing improved amorphous silicon layers.